1. Field of the Invention
The present invention relates generally to the semiconductor technology, and more particularly, to a method for fabricating a high-performance metal-oxide-semiconductor (MOS) transistor device.
2. Description of the Prior Art
A conventional MOS transistor generally includes a semiconductor substrate, a source region, a drain region, a channel between the source region and the drain region, and a gate located above the channel. The gate typically comprises a gate dielectric layer and a gate conductive layer positioned on the gate dielectric layer. Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of the carriers in the channel. Therefore, how to improve the carrier mobility so as to increase the speed and performance of MOS transistors has become a major topic for study in the semiconductor field.
It is known in the art to produce a mechanical stress or strain in the channel in order to increase the carrier mobility in the channel of an MOS transistor. For example, a compressive strained channel, such as a silicon germanium (SiGe) channel layer may be grown on silicon, which can significantly enhance hole mobility. A tensile strained channel, such as a thin silicon channel layer may be grown on silicon germanium to achieves electron mobility enhancement. Another prior art method of obtaining a strained channel is to epitaxially grow a SiGe layer adjacent to the spacers within the semiconductor substrate after forming the spacer. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxial silicon layer due to the silicon germanium, which has a larger lattice constant than that of silicon, and, as a result, the band structure alters, and the carrier mobility increases.
Another approach to the introduction of stress is the stress memorization technique (SMT), which has been employed in 65 nm semiconductor manufacturing processes for enhancing device performance. The SMT generally includes selectively depositing a stressed nitride layer on the gate electrode as a stressor after pre-amorphization implant. The stressed nitride layer is removed after the thermal activation procedures. The stress modulation effect is enhanced and memorized to affect the channel stress underneath the re-crystallized gate electrode after removal of the nitride layer.
However, the above-mentioned prior art has several drawbacks. For example, after the introduction of the stress either by way of the SiGe strained silicon channel technique or by way of SMT stress introduction process, silicon dislocation defects are observed in the silicon substrate, which adversely affects the yield of the manufacturing process.